1. Field of the Invention
This invention relates to a fail memory equipment in a memory tester especially in the form of an integrated circuit (IC) which improves efficiency and effectiveness of storage of results of testing various types of semiconductor memories.
2. Description of the Prior Art
Japanese Patent Publication No. 13958/82 published on Mar. 20, 1982 discloses a fail memory equipment in an IC memory tester.
In the past, the fail memory equipment typically has a storage capacity which is equal to or larger than that of a memory to be tested. For example, one type of the fail memory equipment has a large capacity by utilizing a plurality of memory blocks each having memory cells of a small capacity which are accessible at a high speed, so as to store results (data) of a tester operating at a maximum test speed. Another type uses a plurality of memory blocks each having memory cells of large capacity and low power consumption which are accessible at a low speed and has a peripheral circuit which is devised to operate in an interleave mode so as to fetch in parallel results (data) of a tester operating at a high speed.
The former type using the high speed memory cells of small capacity is highly evaluated in its increased speed but is disadvantageous in that it needs a great number of memory cells and high power consumption and becomes expensive.
In the latter type, of all the memory cells, cells actually used is decreased in number in proportion to an increase in the number of interleaved stages and the effect of high speed due to the interleave mode cannot lead to an improvement in utilization efficiency of the memory blocks. In addition, as the capacity of a memory to be tested increases and the number of test data carrying channels (multi-channel) increases to meet simultaneous tests of a great number of memories, the number of memory cells must be increased by the multiple of the number of interleaved stages, resulting in an extensively increased hardware scale of the fail memory equipment.